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document no. e0490e30 (ver. 3.0) date published september 2004 (k) japan url: http://www.elpida.com ? elpida memory, inc. 2004 preliminary data sheet 512m bits mobile ram mcp 2 pcs of 256mb components edl5132cbma (16m words 32 bits) description the edl5132cbma is a 512m bits mobile ram mcp (multi chip package) organized as 4,194,304 words 32 bits 4 banks, 2 pieces of 256m bits mobile ram in one package. it is packaged in 90-ball fbga. features ? low voltage power supply ? vdd: 1.7v to 1.95v ? vddq: 1.7v to 1.95v ? wide temperature range ( ? 25 c to 85 c) ? programmable partial array self refresh ? programmable driver strength ? auto temperature compensated self refresh by built-in temperature sensor. ? deep power down mode ? fully synchronous dynamic ram, with all signals referenced to a positive clock edge ? pulsed interface ? possible to assert random column address in every cycle ? quad internal banks controlled by ba0 and ba1 ? byte control by dqm ? wrap sequence = sequential/ interleave ? /cas latency (cl) = 2, 3 ? automatic precharge and controlled precharge ? auto refresh and self refresh ? 32 organization ? 8,192 refresh cycles/64ms ? burst termination by burst stop command and precharge command ? fbga package with lead free solder (sn-ag-cu) pin configurations /xxx indicates active low signal. dq26 1 a b c d e f g h j k l m n p r 23456789 dq28 vssq vssq vddq vss a4 a7 clk dq24 vddq dq27 dq29 dq31 dqm3 a5 a8 cke vss vssq dq25 dq30 nc a3 a6 a12 a9 vdd vddq dq22 dq17 nc a2 a10 nc ba0 dq23 vssq dq20 dq18 dq16 dqm2 a0 ba1 /cs dq21 dq19 vddq vddq vssq vdd a1 a11 /ras (top view) dqm1 nc nc /cas /we dqm0 vddq dq8 vss vdd dq7 vssq vssq dq10 dq9 dq6 dq5 vddq vssq dq12 dq14 dq1 dq3 vddq dq11 vddq vssq vddq vssq dq4 dq13 dq15 vss vdd dq0 dq2 90-ball fbga address inputs bank select address data-input/output chip select row address strobe column address strobe write enable dq mask enable clock enable clock input power supply ground power supply for dq ground for dq no connection a0 to a12 ba0, ba1 dq0 to dq31 /cs /ras /cas /we dqm0 to dqm3 cke clk vdd vss vddq vssq nc
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 2 ordering information part number organization (words bits) internal banks clock frequency mhz (max.) /cas latency package EDL5132CBMA-10-E 16m 32 4 100 3 90-ball fbga part number environment code e: lead free elpida memory density / bank 51: 512m /4-bank bit organization 32: x32 voltage, interface c: vdd = 1.8v, vddq = 1.8v, lvcmos die rev. package ma: stacked fbga speed 10: 100mhz/cl3 product code l: mobile ram type d: monolithic device e d l 51 32 c b ma - 10 - e
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 3 contents description.................................................................................................................... .................................1 features....................................................................................................................... ..................................1 pin configurations ............................................................................................................. ............................1 ordering information........................................................................................................... ...........................2 part number .................................................................................................................... ..............................2 electrical specifications...................................................................................................... ...........................4 block diagram .................................................................................................................. ...........................10 pin function................................................................................................................... ..............................11 command operation .............................................................................................................. .....................13 truth table .................................................................................................................... ..............................17 simplified state diagram ....................................................................................................... ......................23 initialization ................................................................................................................. .................................24 programming mode registers..................................................................................................... ................24 address bits of bank-select and precharge ...................................................................................... .........28 operation of the mobile ram .................................................................................................... ..................29 timing waveforms............................................................................................................... ........................37 package drawing ................................................................................................................ ........................59 recommended soldering conditions ............................................................................................... ...........60
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 4 electrical specifications ? all voltages are referenced to vss (gnd). ? after power up, wait more than 200 s and then, execute power on sequence and two auto refresh before proper device operation is achieved. absolute maximum ratings parameter symbol rating unit note voltage on any pin relative to vss vt ?0.5 to +2.6 v supply voltage relative to vss vdd, vddq ?0.5 to +2.6 v short circuit output current ios 50 ma power dissipation pd 1.0 w operating ambient temperature ta ?25 to +85 c storage temperature tstg ?55 to +125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc operating conditions (ta = ?25 to +85 c) parameter symbol min. typ. max. unit notes supply voltage vdd 1.7 1.8 1.95 v vss, vssq 0 0 0 v dq supply voltage vddq 1.7 1.8 1.95 v input high voltage vih 0.8 vddq ? vddq + 0.3 v 1 input low voltage vil ?0.3 ? 0.3 v 2 notes: 1. vih (max.) = 2.6v (pulse width 5ns) 2. vil (min.) = ?1.0v (pulse width 5ns)
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 5 dc characteristics 1 (ta = ?25 to +85 c, vdd = vddq = 1.7v to 1.95v, vss, vssq = 0v) parameter /cas latency symbol grade max. unit test condition notes operating current (cl = 2) idd1 80 ma 1 (cl = 3) idd1 80 ma burst length = 1 trc trc min., io = 0ma, one bank active standby current in power down idd2p 1.2 ma cke vil max., tck = 15ns standby current in power down (input signal stable) idd2ps 1 ma cke vil max., tck = standby current in non power down idd2n 6 ma cke vih min., tck = 15ns, /cs vih min., input signals are changed one time during 30ns. standby current in non power down (input signal stable) idd2ns 4 ma cke vih min., tck = , input signals are stable. active standby current in power down idd3p 2 ma cke vil max., tck = 15ns active standby current in power down (input signal stable) idd3ps 1.6 ma cke vil max., tck = active standby current in non power down idd3n 30 ma cke vih min., tck = 15 ns, /cs vih min., input signals are changed one time during 30ns. active standby current in non power down (input signal stable) idd3ns 10 ma cke vih min., tck = , input signals are stable. burst operating current (cl = 2) idd4 90 ma tck tck min., iout = 0ma, all banks active 2 (cl = 3) idd4 120 ma refresh current (cl = 2) idd5 110 ma trc trc min. 3 (cl = 3) idd5 110 ma standby current in deep power down mode idd7 20 a cke 0.2v self refresh current symbol grade typ. max. unit condition notes pasr="000" (full) idd6 ? ? 800 a ta 85c +0c/ ? 15c, cke 0.2v 4 pasr="001" (2bk) ? ? 600 a pasr="010" (1bk) ? ? 500 a pasr="000" (full) idd6 400 ? a ta 45c, cke 0.2v 4 pasr="001" (2bk) 360 ? a pasr="010" (1bk) 300 ? a notes: 1. idd1 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, idd1 is measured on condition that addresses are changed only one time during tck (min.). 2. idd4 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, idd4 is measured on condition that addresses are changed only one time during tck (min.). 3. idd5 is measured on condition that addresses are changed only one time during tck (min.). 4. idd6 is specified when self refresh state is maintained long enough under the specified ta condition, after a busy sequence of read and write operations.
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 6 dc characteristics 2 (ta = ?25 to +85 c, vdd = vddq = 1.7v to 1.95v, vss, vssq = 0v) parameter symbol min. max. unit test condition note input leakage current ili ?2.0 2.0 a 0 vin vddq output leakage current ilo ?1.5 1.5 a 0 vout vddq, dq = disable output high voltage voh vddq ? 0.2 ? v ioh = ?0.1 ma output low voltage vol ? 0.2 v iol = 0.1 ma pin capacitance (ta = 25c, f = 1mhz) parameter symbol pins min. typ. max. unit note input capacitance ci1 clk 4.0 ? 7.0 pf ci2 address, cke, /cs, /ras, /cas, /we 4.0 ? 7.6 pf cl3 dqm 2.0 ? 3.8 pf data input/output capacitance ci/o dq 6.0 ? 7.5 pf
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 7 ac characteristics (ta = ?25 to +85 c, vdd = vddq = 1.7v to 1.95v, vss, vssq = 0v) test conditions ? ac high level input voltage / low level input voltage: 1.6 / 0.2v ? input timing measurement reference level: 0.9v ? transition time (input rise and fall time): 1ns ? output timing measurement reference level: 0.9v t ck t ch t cl 1.6 v 0.9 v 0.2 v clk 1.6 v 0.9 v 0.2 v input t setup t hold output t ac t oh
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 8 synchronous characteristics parameter symbol min. max. unit note clock cycle time (cl= 2) tck2 15 ? ns (cl= 3) tck3 10 ? ns access time from clk (cl= 2) tac2 ? 9 ns 1 (cl= 3) tac3 ? 7 ns 1 clk high level width tch 3 ? ns clk low level width tcl 3 ? ns data-out hold time toh 3 ? ns 1 data-out low-impedance time tlz 0 ? ns data-out high-impedance time (cl= 2) thz2 3 9 ns (cl= 3) thz3 3 7 ns data-in setup time tds 2 ? ns data-in hold time tdh 1 ? ns address setup time tas 2 ? ns address hold time tah 1 ? ns cke setup time tcks 2 ? ns cke hold time tckh 1 ? ns cke setup time (power down exit) tcksp 2 ? ns command (/cs, /ras, /cas, /we, dqm) setup time tcms 2 ? ns command (/cs, /ras, /cas, /we, dqm) hold time tcmh 1 ? ns note: 1. output load. output z = 50 ? output load
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 9 asynchronous characteristics parameter symbol min. max. unit note act to ref/act command period (operation) trc 90 ? ns act to ref/act command period (refresh) trc1 110 ? ns self refresh exit to ref/act command period trc2 120 ? ns act to pre command period tras 60 120000 ns pre to act command period trp 30 ? ns delay time act to read/write command trcd 30 ? ns act (one) to act (another) command period trrd 2 ? clk data-in to pre command period tdpl 2 ? clk data-in to act (ref) command period (auto precharge) (cl = 2) tdal2 2clk + 30 ? ns (cl = 3) tdal3 2clk + 30 ? ns mode register set cycle time trsc 2 ? clk transition time tt 1 30 ns refresh time (8,192 refresh cycles) tref ? 64 ms
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 10 block diagram a0 to a12 clk, cke dq0 to dq15 dqm0 to dqm1 dq16 to dq31 dqm2 to dqm3 /cs, /ras, /cas /we 256m (x16) bits mobile ram 256m (x16) bits mobile ram
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 11 pin function clk (input pin) clk is the master clock input. other inputs signals are referenced to the clk rising edge. cke (input pins) cke determine validity of the next clk (clock). if cke is high, the next clk rising edge is valid; otherwise it is invalid. if the clk rising edge is invalid, the internal clock is not issued and the mobile ram suspends operation. when the mobile ram is not in burst mode and cke is negated, the device enters power down mode. during power down mode, cke must remain low. /cs (input pins) /cs low starts the command input cycle. when /cs is high, commands are ignored but operations continue. /ras, /cas, and /we (input pins) /ras, /cas and /we have the same symbols on conventional dram but different functions. for details, refer to the command table. a0 to a12 (input pins) row address is determined by a0 to a12 at the clk (clock) rising edge in the active command cycle. it does not depend on the bit organization. column address (see ?address pins table?) is determined by a0 to a8 at the clk rising edge in the read or write command cycle. [address pins table] address (a0 to a12) part number row addre sss column address edl5132cb ax0 to ax12 ay0 to ay8 a10 defines the precharge mode. when a10 is high in the precharge command cycle, all banks are precharged; when a10 is low, only the bank selected by ba0 and ba1 is precharged. when a10 is high in read or write command cycle, the precharge starts automatically after the burst access. ba0 and ba1 (input pin) ba0 and ba1 are bank select signal. (see bank select signal table) [bank select signal table] ba0 ba1 bank a l l bank b h l bank c l h bank d h h remark: h: vih. l: vil.
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 12 dqm0 to dqm3 (input pins) dqm controls i/o buffers. in read mode, dqm controls the output buffers like a conventional /oe pin. dqm high and dqm low turn the output buffers off and on, respectively. the dqm latency for the read is two clocks. in write mode, dqm controls the word mask. input data is written to the memory cell if dqm is low but not if dqm is high. the dqm latency for the write is zero. each dqm pin corresponds to eight dq pins, respectively (see dqm correspondence table). [dqm correspondence table] dq mask enabe dqs dqm0 dq0 to dq7 dqm1 dq8 to dq15 dqm2 dq16 to dq23 dqm3 dq24 to dq31 dq0 to dq31 (input/output pins) dq pins have the same function as i/o pins on a conventional dram. vdd, vss, vddq, vssq (power supply) vdd and vss are power supply pins for internal circuits. vddq and vssq are power supply pins for the output buffers.
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 13 command operation extended mode register set command (/cs, /ras, /cas, /we, ba0 = low, ba1 = high) the mobile ram has an extended mode register that defines low power functions. in this command, a0 through a12 are the data input pins. after power on, the extended mode register set command must be executed to fix low power functions. the extended mode register can be set only when all banks are in idle state. during trsc following this command, the mobile ram can not accept any other commands. /we /cas /ras /cs cke clk h add a10 ba0 ba1 extended mode register set command mode register set command (/cs, /ras, /cas, /we, ba0, ba1 = low) the mobile ram has a mode register that defines how the device operates. in this command, a0 through a12 are the data input pins. after power on, the mode register set command must be executed to initialize the device. the mode register can be set only when all banks are in idle state. during trsc following this command, the mobile ram cannot accept any other commands. /we /cas /ras /cs cke clk h add a10 ba0 ba1 mode register set command activate command (/cs, /ras = low, /cas, /we = high) the mobile ram has four banks, each with 8,192 rows. this command activates the bank selected by ba0 and ba1 and a row address selected by a0 through a12. this command corresponds to a conventional dram's /ras falling. /we /cas /ras /cs cke clk h add a10 ba0, ba1 row row activate command
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 14 precharge command (/cs, /ras, /we = low, /cas = high) this command begins precharge operation of the bank selected by ba0 and ba1. when a10 is high, all banks are precharged, regardless of ba0 and ba1. when a10 is low, only the bank selected by ba0 and ba1 is precharged. after this command, the mobile ram can?t accept the activate command to the precharging bank during trp (precharge to activate command period). this command corresponds to a conventional dram?s /ras rising. /we /cas /ras /cs cke clk h add a10 ba0, ba1 (precharge select) precharge command write command (/cs, /cas, /we = low, /ras = high) this command sets the burst start address given by the column address to begin the burst write operation. the first write data in burst mode can input with this command with subsequent data on following clocks. /we /cas /ras /cs cke clk h add a10 ba0, ba1 col. write command read command (/cs, /cas = low, /ras, /we = high) read data is available after /cas latency requirements have been met. this command sets the burst start address given by the column address. /we /cas /ras /cs cke clk h add a10 ba0, ba1 col. read command
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 15 auto refresh command (/cs, /ras, /cas = low, /we, cke = high) this command is a request to begin the auto refresh operation. the refresh address is generated internally. before executing auto refresh, all banks must be precharged. after this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. during trc1 period (from refresh command to refresh or activate command), the mobile ram cannot accept any other command add a10 ba0, ba1 /we /cas /ras /cs cke clk h auto refresh command self refresh entry command (/cs, /ras, /cas, cke = low, /we = high) after the command execution, self refresh operation continues while cke remains low. when cke goes high, the mobile ram exits the self refresh mode. during self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control. before executing self refresh, all banks must be precharged. /we /cas /ras /cs cke clk add a10 ba0, ba1 self refresh entry command power down entry command (/cs, cke = low, /ras, /cas, /we = high) after the command execution, power down mode continues while cke remains low. when cke goes high, the mobile ram exits the power down mode. before executing power down, all banks must be precharged. /we /cas /ras /cs cke clk add a10 ba0, ba1 power down entry command
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 16 deep power down entry command( /cs, cke, /we = low, /ras, /cas = high) after the command execution, deep power down mode continues while cke remains low. when cke goes high, the mobile ram exits the deep power down mode. before executing deep power down, all banks must be precharged. /we /cas /ras /cs cke clk add a10 ba0, ba1 deep power down entry command burst stop command (/cs = /we = low, /ras, /cas = high) this command can stop the current burst operation. /we /cas /ras /cs cke clk add a10 ba0, ba1 h burst stop command no operation (/cs = low, /ras, /cas, /we = high) this command is not an execution command. no operations begin or terminate by this command. /we /cas /ras /cs cke clk h add a10 ba0, ba1 no operation
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 17 truth table command truth table cke a11, a12, function symbol n ? 1 n /cs /ras /cas /we ba1 ba0 a10 a9 - a0 device deselect desl h h no operation nop h l h h h burst stop bst h h l h h l read read h l h l h v v l v read with auto precharge reada h l h l h v v h v write writ h l h l l v v l v write with auto precharge writa h l h l l v v h v bank activate act h l l h h v v v v precharge select bank pre h l l h l v v l precharge all banks pall h l l h l h mode register set mrs h l l l l l l l v extended mode register set emrs h l l l l h l l v remark: h: vih. l: vil. : vih or vil, v = valid data dqm truth table cke dqm function symbol n ? 1 n 0 1 2 3 data write / output enable enb h l l l l data mask / output disable mask h h h h h dq0 to dq7 write enable/output enable enb0 h l dq8 to dq15 write enable/output enable enb1 h l dq16 to dq23 write enable/output enable enb2 h l dq24 to dq31 write enable/output enable enb3 h l dq0 to dq7 write inhibit/output disable mask0 h h dq8 to dq15 write inhibit/output disable mask 1 h h dq16 to dq23 write inhibit/output disable mask 2 h h dq24 to dq31 write inhibit/output disable mask 3 h h remark: h: vih. l: vil. : vih or vil
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 18 cke truth table cke current state function symbol n ? 1 n /cs /ras /cas /we address activating clock suspend mode entry h l any clock suspend mode l l clock suspend clock suspend mode exit l h idle auto refresh command ref h h l l l h idle self refresh entry self h l l l l h idle power down entry pd h l l h h h h l h idle deep power down entry dpd h l l h h l self refresh self refresh exit l h l h h h l h h power down power down exit l h l h h h l h h deep power down deep power down exit l h remark: h: vih. l: vil. : vih or vil
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 19 function truth table current state /cs /ras /cas /we address command action notes idle h desl nop l h h h nop nop l h h l bst nop l h l h ba, ca, a10 read/reada illegal 2 l h l l ba, ca, a10 writ/ writa illegal 2 l l h h ba, ra act row activating l l h l ba, a10 pre/pall nop l l l h ref auto refresh l l l l oc, ba1= l mrs mode register set l l l l oc, ba1= h emrs extended mode register set row active h desl nop l h h h nop nop l h h l bst nop l h l h ba, ca, a10 read/reada begin read 3 l h l l ba, ca, a10 writ/ writa begin write 3 l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall precharge/precharge all banks 4 l l l h ref illegal l l l l oc, ba mrs/emrs illegal read h desl continue burst to end row active l h h h nop continue burst to end row active l h h l bst burst stop row active l h l h ba, ca, a10 read/reada terminate burst, begin new read 5 l h l l ba, ca, a10 writ/writa terminate burst, begin write 5, 6 l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall terminate burst precharging l l l h ref illegal l l l l oc, ba mrs/emrs illegal write h desl continue burst to end write recovering l h h h nop continue burst to end write recovering l h h l bst burst stop row active l h l h ba, ca, a10 read/reada terminate burst, start read : determine ap 5, 6 l h l l ba, ca, a10 writ/writa terminate burst, new write : determine ap 5 l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall terminate burst precharging 7 l l l h ref illegal l l l l oc, ba mrs/emrs illegal
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 20 current state /cs /ras /cas /we address command action notes read with auto h desl continue burst to end precharging precharge l h h h nop continue burst to end precharging l h h l bst illegal l h l h ba, ca, a10 read/reada illegal 2 l h l l ba, ca, a10 writ/ writa illegal 2 l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall illegal 2 l l l h ref illegal l l l l oc, ba mrs/emrs illegal write with auto precharge h desl continue burst to end write recovering with auto precharge l h h h nop continue burst to end write recovering with auto precharge l h h l bst illegal l h l h ba, ca, a10 read/reada illegal 2 l h l l ba, ca, a10 writ/ writa illegal 2 l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall illegal 2 l l l h ref illegal l l l l oc, ba mrs/emrs illegal precharging h desl nop enter idle after trp l h h h nop nop enter idle after trp l h h l bst illegal l h l h ba, ca, a10 read/reada illegal 2 l h l l ba, ca, a10 writ/writa illegal 2 l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall nop enter idle after trp l l l h ref illegal l l l l oc, ba mrs/emrs illegal row activating h desl nop enter bank active after trcd l h h h nop nop enter bank active after trcd l h h l bst illegal l h l h ba, ca, a10 read/reada illegal 2 l h l l ba, ca, a10 writ/writa illegal 2 l l h h ba, ra act illegal 2, 8 l l h l ba, a10 pre/pall illegal 2 l l l h ref illegal l l l l oc, ba mrs/emrs illegal
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 21 current state /cs /ras /cas /we address command action notes write recovering h desl nop enter row active after tdpl l h h h nop nop enter row active after tdpl l h h l bst nop enter row active after tdpl l h l h ba, ca, a10 read/reada begin read 6 l h l l ba, ca, a10 writ/ writa begin new write l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall illegal 2 l l l h ref illegal l l l l oc, ba mrs/emrs illegal write recovering h desl nop enter precharge after tdpl with auto l h h h nop nop enter precharge after tdpl precharge l h h l bst nop enter row active after tdpl l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writa illegal 2, 6 l l h h ba, ra act illegal 2 l l h l ba, a10 pre/pall illegal 2 l l l h ref illegal l l l l oc, ba mrs/emrs illegal refresh h desl nop enter idle after trc1 l h h h nop nop enter idle after trc1 l h h l bst nop enter idle after trc1 l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writa illegal l l h h ba, ra act illegal l l h l ba, a10 pre/pall illegal l l l h ref illegal l l l l oc, ba mrs/emrs illegal mode register h desl nop enter idle after trsc accessing l h h h nop nop enter idle after trsc l h h l bst nop enter idle after trsc l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writa illegal l l h h ba, ra act illegal l l h l ba, a10 pre/pall illegal l l l h ref illegal l l l l oc, ba mrs/emrs illegal
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 22 current state /cs /ras /cas /we address command action notes extended mode h desl nop enter idle after trsc register l h h h nop nop enter idle after trsc accessing l h h l bst nop enter idle after trsc l h l h ba, ca, a10 read/reada illegal l h l l ba, ca, a10 writ/writa illegal l l h h ba, ra act illegal l l h l ba, a10 pre/pall illegal l l l h ref illegal l l l l oc, ba0,ba1 mrs/emrs illegal remark: h: vih. l: vil. : vih or vil, v = valid data ba: bank address, ca: column address, ra: row address, oc: op-code notes: 1. all entries assume that cke is active (cke n-1 =cke n =h). 2. illegal to bank in specified states; function may be legal in the bank indicated by bank address (ba), depending on the state of that bank. 3. illegal if trcd is not satisfied. 4. illegal if tras is not satisfied. 5. must satisfy burst interrupt condition. 6. must satisfy bus contention, bus turn around, and/or write recovery requirements. 7. must mask preceding data which don't satisfy tdpl. 8. illegal if trrd is not satisfied.
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 23 simplified state diagram cke cke cke cke cke cke cke cke precharge auto precharge pre read with auto precharge read bst bst pre (precharge termination) pre (precharge termination) act mrs ref cke cke self self exit idle mode register set extended mode register set cbr (auto) refresh row active self refresh power down active power down precharge emrs read reada read suspend reada suspend write writea write suspend writea suspend power on write read automatic sequence manual input cke cke read write write with write deep power down dpd dpd exit
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 24 initialization the synchronous dram is initialized in the power-on sequence according to the following. (1) to stabilize internal circuits, when power is applied, a 200 s or longer pause must precede any signal toggling. (2) after the pause, all banks must be precharged using the precharge command (the precharge all banks command is convenient). (3) once the precharge is completed and the minimum trp is satisfied, two or more auto refresh must be performed. (4) both the mode register and the extended mode register must be programmed. after the mode register set cycle or the extended mode register set cycle, trsc (2 clk minimum) pause must be satisfied. remarks: 1 the sequence of auto refresh, mode register programming and extended mode register programming above may be transposed. 2 cke and dqm must be held high until the precharge command is issued to ensure data-bus high-z. programming mode registers the mode register and extended mode register are programmed by the mode register set command and extended mode register command, respectively using address bits a12 through a0, ba0 and ba1 as data inputs. the registers retain data until they are re-programmed, or the device enters into the deep power down or the device loses power. mode register the mode register has three fields; options : a12 through a7 /cas latency : a6 through a4 wrap type : a3 burst length : a2 through a0 following mode register programming, no command can be issued before at least 2 clk have elapsed. /cas latency /cas latency is the most critical of the parameters being set. it tells the device how many clocks must elapse before the data will be available. the value is determined by the frequency of the clock and the speed grade of the device. burst length burst length is the number of words that will be output or input in a read or write cycle. after a read burst is completed, the output bus will become high-z. the burst length is programmable as 1, 2, 4, 8 or full page. wrap type (burst sequence) the wrap type specifies the order in which the burst data will be addressed. this order is programmable as either ?sequential? or ?interleave?. the method chosen will depend on the type of cpu in the system. some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing. ?burst length sequence? shows the addressing sequence for each burst length using them. both sequences support bursts of 1, 2, 4 and 8. additionally, sequence supports the full page length.
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 25 extended mode register the extended mode register has four fields; options : a12 through a7, a4, a3 auto temperature compensated self refresh : a9 driver strength : a6 through a5 partial array self refresh : a2 through a0 following extended mode register programming, no command can be issued before at least 2 clk have elapsed. driver strength by setting specific parameter on a6 and a5, driving capability of data output drivers is selected. auto temperature compensated self refresh (atcsr) with the built-in temperature sensor, the internal self refresh frequency is controlled autonomously. partial array self refresh memory array size to be refreshed during self refresh operation is programmable in order to reduce power. data outside the defined area will not be retained during self refresh.
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 26 mode register definition wt = 1 1 2 4 8 r r r r bl wt 0 0 0 0 0 mode register set wt = 0 1 2 4 8 r r r full page bits2-0 000 001 010 011 100 101 110 111 burst length sequential interleave 0 1 wrap type a0 a1 a2 a3 a4 a5 a7 a6 a8 a9 a10 a11 0 0 remark r : reserved ltmode pasr ds 000 0 atcsr 0 extended mode register set refresh array all banks bank a & bank b (ba1=0) bank a (ba0=ba1=0) r r r r r bits2-0 000 001 010 011 100 101 110 111 partial array self refresh driver strength ba1 ba0 1 0 /cas latency r r 2 3 r r r r bits6-4 000 001 010 011 100 101 110 111 latency mode a12 0 a0 a1 a2 a3 a4 a5 a7 a6 a8 a9 a10 a11 ba1 ba0 0 strength normal 1/2 strength 1/4 strength 1/8 strength bits6-5 00 01 10 11 a12 0 atcsr enable r bit9 0 1 atcsr
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 27 burst length and sequence [burst of two] starting address (column address a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 0 0, 1 0, 1 1 1, 0 1, 0 [burst of four] starting address (column address a1 ? a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 00 0, 1, 2, 3 0, 1, 2, 3 01 1, 2, 3, 0 1, 0, 3, 2 10 2, 3, 0, 1 2, 3, 0, 1 11 3, 0, 1, 2 3, 2, 1, 0 [burst of eight] starting address (column address a2 ? a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 full page burst is an extension of the above tables of sequential addressing, with the length being 512.
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 28 address bits of bank-select and precharge a11 a10 a9 a8 a7 a6 a4 a5 a3 a2 a1 a0 row (activate command) a11 a10 a9 a8 a7 a6 a4 a5 a3 a2 a1 a0 (precharge command) disables auto-precharge (end of burst) 0 enables auto-precharge (end of burst) 1 a11 a10 a9 a8 a7 a6 a4 a5 a3 a2 a1 a0 col. (/cas strobes) x : don?t care select bank a ?activate? command 0 select bank b ?activate? command 0 1 1 0 1 0 1 ba1 ba0 ba1 ba0 ba1 ba0 result select bank c ?activate? command select bank d ?activate? command enables read/write commands for bank a 0 enables read/write commands for bank b 0 1 1 0 1 0 1 result enables read/write commands for bank c enables read/write commands for bank d result precharge bank a precharge bank b precharge bank c precharge bank d precharge all banks a10 0 0 0 0 1 0 0 1 1 x 0 1 0 1 x ba1 ba0 ba1 ba0 ba1 ba0 a12 a12 a12
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 29 operation of the mobile ram precharge the precharge command can be issued anytime after tras min. is satisfied. soon after the precharge command is issued, precharge operation performed and the synchronous dram enters the idle state after trp is satisfied. the parameter trp is the time required to perform the precharge. the earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is as follows. t0 t1 t2 t3 t4 t5 t6 t7 burst length=4 read read q1 q2 q3 q4 pre hi-z q1 q2 q3 q4 pre hi-z (t ras must be satisfied) clk command /cas latency = 2 dq command /cas latency = 3 dq t8 precharge in order to write all data to the memory cell correctly, the asynchronous parameter tdpl must be satisfied. the tdpl (min.) specification defines the earliest time that a precharge command can be issued. minimum number of clocks is calculated by dividing tdpl (min.) with clock cycle time. in summary, the precharge command can be issued relative to reference clock that indicates the last data word is valid. in the following table, minus means clocks before the reference; plus means time after the reference. /cas latency read write 2 -1 +tdpl(min.) 3 -2 +tdpl(min.)
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 30 auto precharge during a read or write command cycle, a10 controls whether auto precharge is selected. a10 high in the read or write command (read with auto precharge command or write with auto precharge command), auto precharge is selected and begins automatically. the tras must be satisfied with a read with auto precharge or a write with auto precharge operation. in addition, the next activate command to the bank being precharged cannot be executed until the precharge cycle ends. in read cycle, once auto precharge has started, an activate command to the bank can be issued after trp has been satisfied. in write cycle, the tdal must be satisfied to issue the next activate command to the bank being precharged. the timing that begins the auto precharge cycle depends on whether read or write cycle. read with auto precharge during a read cycle, the auto precharge begins one clock earlier (/cas latency of 2) or two clocks earlier (/cas latency of 3) the last data word output. qb1 qb2 qb3 qb4 auto precharge starts reada b hi-z qb1 qb2 qb3 qb4 auto precharge starts reada b hi-z dq command dq command /cas latency = 2 /cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4 (t ras must be satisfied) t9 read with auto precharge remark: reada means read with auto precharge write with auto precharge during a write cycle, the auto precharge starts at the timing of 2 clocks after the last data word input to the device. db1 db2 db3 db4 auto precharge starts writa b hi-z dq command clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4 (t ras must be satisfied) write with auto precharge remark: writa means write with auto precharge
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 31 read / write command interval read to read command interval during a read cycle, when new read command is issued, it will be effective after /cas latency, even if the previous read operation does not completed. read will be interrupted by another read. the interval between the commands is 1 cycle minimum. each read command can be issued in every clock without any restriction. qb1 qb2 qb3 qb4 hi-z read a dq command clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4, /cas latency = 2 read b qa1 1cycle t9 read to read command interval write to write command interval during a write cycle, when a new write command is issued, the previous burst will terminate and the new burst will begin with a new write command. write will be interrupted by another write. the interval between the commands is minimum 1 cycle. each write command can be issued in every clock without any restriction. db1 db2 db3 db4 hi-z write a dq command clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4 write b da1 1cycle write to write command interval
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 32 write to read command interval write command and read command interval is also 1 cycle. only the write data before read command will be written. the data bus must be high-z at least one cycle prior to the first dout. qb1 qb2 qb3 qb4 write a hi-z qb1 qb2 qb3 qb4 write a hi-z dq command dq command /cas latency = 2 /cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4 da1 da1 read b read b write to read command interval
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 33 read to write command interval during a read cycle, read can be interrupted by write. the read and write command interval is 1 cycle minimum. there is a restriction to avoid data conflict. the data bus must be high-z using dqm before write. d1 d2 d3 d4 read dq command clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 4 write dqm hi-z 1cycle read to write command interval 1 read can be interrupted by write. dqm must be high at least 3 clocks prior to the write command. clk t0 t2 t1 t3 t4 t5 t6 t7 t8 burst length = 8 t9 q1 q2 q3 read dq command d1 d2 d3 write dqm hi-z is necessary q1 q2 read dq command d1 d2 d3 write dqm hi-z is necessary /cas latency = 2 /cas latency = 3 read to write command interval 2
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 34 burst termination there are two methods to terminate a burst operation other than using a read or a write command. one is the burst stop command and the other is the precharge command. burst termination in read cycle during a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus goes to high-z after the /cas latency from the burst stop command. read command clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x q1 q2 q3 dq /cas latency = 2 hi-z q1 q2 q3 dq /cas latency = 3 hi-z bst burst termination in read cycle remark: bst: burst stop command burst termination in write cycle during a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to high-z at the same clock with the burst stop command. d2 d3 d4 write dq command clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x bst hi-z d1 burst termination in write cycle remark: bst: burst stop command
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 35 precharge termination in read cycle during a read cycle, the burst read operation is terminated by a precharge command. when the precharge command is issued, the burst read operation is terminated and precharge starts. the same bank can be activated again after trp from the precharge command. to issue a precharge command, tras must be satisfied. when /cas latency is 2, the read data will remain valid until one clock after the precharge command. read clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x, /cas latency = 2 q1 dq command q2 q3 q4 act t rp pre hi-z (t ras must be satisfied) precharge termination in read cycle (cl = 2) when /cas latency is 3, the read data will remain valid until two clocks after the precharge command. read clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x, /cas latency = 3 dq command q1 q2 q3 act t rp pre hi-z t8 q4 (t ras must be satisfied) precharge termination in read cycle (cl = 3)
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 36 precharge termination in write cycle during a write cycle, the burst write operation is terminated by a precharge command. when the precharge command is issued, the burst write operation is terminated and precharge starts. the same bank can be activated again after trp from the precharge command. to issue a precharge command, tras must be satisfied. the write data written up to two clocks prior to the precharge command will be correctly stored. however, invalid data may be written at the same clock as the precharge command and one clock before the precharge command. to prevent this from happening, dqm must be high and mask the invalid data. write clk t0 t2 t1 t3 t4 t5 t6 t7 burst length = x, /cas latency = 3 dq command d1 d2 d3 act dqm t rp t dpl pre hi-z d5 t8 d4 (t ras must be satisfied) precharge termination in write cycle
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 37 timing waveforms ac parameters for read timing with manual precharge t oh t lz t ac t oh t ac t ac t oh t oh t ac t hz t ras t rc ba0 t ckh t rp t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 clk cke /cs /ras /cas /we ba1 a10 add dqm dq t rcd t cks t ch t cl t ck t cms t cmh t as t ah l hi-z activate command for bank a precharge command for bank a read command for bank a activate command for bank a [burst length = 4, /cas latency = 3]
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 38 ac parameters for read timing with auto precharge t cks t oh t lz t ac t oh t ac t ac t oh t oh t ac t hz t ras t rrd t rc ba0 t ckh t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 clk cke /cs /ras /cas /we ba1 a10 add dqm dq t rcd t ch t cl t ck t cms t cmh t as t ah l hi-z auto precharge start for bank c activate command for bank c activate command for bank d read with auto precharge command for bank c activate command for bank c [burst length = 4, /cas latency = 3]
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 39 ac parameters for write timing t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 clk cke ba0 a10 add dqm dq hi-z t as t ah t ds t dh t rcd t dal t rc t rrd t rcd t ras t rc t dpl t rp t ckh t cms t cmh t cks /cs /ras /cas /we ba1 auto precharge start for bank c l activate command for bank c activate command for bank b write command for bank b activate command for bank b write with auto precharge command for bank c precharge command for bank b activate command for bank c [burst length = 4]
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 40 mode register set clk cke /cs /ras /cas /we ba0 a10 add dqm dq ba1 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 hi-z address key t rp precharge all banks command mode register set command activate command is valid h t rsc 2 clk (min.)
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 41 extended mode register set clk cke /cs /ras /cas /we ba0 a10 add dqm dq ba1 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 hi-z address key t rp precharge all banks command extended mode register set command activate command is valid h t rsc 2 clk (min.) power on sequence clk cke /cs /ras /cas /we ba1 a10 add dqm dq hi-z t rsc t rsc address key address key t rp high level is necessary 2 refresh cycles are necessary t rc1 t rc1 precharge all banks command is necessary mode register set command is necessary extended mode register set command is necessary cbr (auto) refresh command is necessary activate command cbr (auto) refresh command is necessary ba0 high level is necessary clock cycle is necessary
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 42 /cs function only /cs signal needs to be issued at minimum rate clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 h l hi-z l ba0 l raa qaa1 qaa2 qaa3 qaa4 dab1 dab2 dab3 dab4 activate command for bank a read command for bank a write command for bank a precharge command for bank a raa caa cab [burst length = 4, /cas latency = 3]
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 43 clock suspension during burst read clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa1 qaa2 qaa3 qaa4 caa ba0 l hi-z raa raa activate command for bank a read command for bank a 1-clock suspended 2-clock suspended 3-clock suspended hi-z (turn off) at the end of burst [burst length = 4, /cas latency = 3] clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa1 qaa2 qaa3 qaa4 caa ba0 l hi-z raa raa activate command for bank a read command for bank a 1-clock suspended 2-clock suspended 3-clock suspended hi-z (turn off) at the end of burst [burst length = 4, /cas latency = 2]
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 44 clock suspension during burst write clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 caa ba0 l hi-z raa raa daa1 daa2 daa3 daa4 activate command for bank a 1-clock suspended 2-clock suspended 3-clock suspended write command for bank a
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 45 power down mode and clock mask clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa3 caa l hi-z raa ba0 t cksp t cksp qaa1 qaa2 valid activate command for bank a power down mode entry active standby power down mode exit read command for bank a clock mask start clock mask end power down mode entry precharge command for bank a precharge standby power down mode exit qaa4 raa [burst length = 4, /cas latency = 3] clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa3 caa l hi-z raa ba0 t cksp t cksp qaa1 qaa2 valid activate command for bank a power down mode entry active standby power down mode exit read command for bank a clock mask start clock mask end power down mode entry precharge command for bank a precharge standby power down mode exit qaa4 raa [burst length = 4, /cas latency = 2]
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 46 auto refresh clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 tn tn + 1tn + 2tn + 3tn + 4tn + 5tn + 6tmtm + 1tm + 2tm + 3tm + 4tm + 5tm + 6tm + 7 ba0 l hi-z t rp h t rc1 t rc1 q1 precharge command (if necessary) cbr (auto) refresh cbr (auto) refresh activate command read command
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 47 self refresh (entry and exit) clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 tn tn + 1tn + 2tmtm + 1tktk + 1tk + 2tk + 3tk + 4 t rp t rc2 t rc2 ba0 precharge command (if necessary) self refresh entry self refresh exit next clock enable self refresh entry (or activate command) activate command self refresh exit next clock enable l hi-z
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 48 deep power down entry clk cke /cs /ras /cas /we ba0 a10 add dqm dq ba1 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 hi-z t rp precharge all banks command deep power down entry l deep power down exit clk cke /cs /ras /cas /we ba1 a10 add dqm dq hi-z t rsc t rsc address key address key t rp 200 high level is necessary 2 refresh cycles are necessary t rc1 t rc1 precharge all banks command is necessary deep power down exit command mode register set command is necessary extended mode register set command is necessary cbr (auto) refresh command is necessary activate command cbr (auto) refresh command is necessary ba0 high level is necessary clock cycle is necessary
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 49 random column read clk cke /cs /ras /cas /we ba1 a10 add dqm dq precharge command for bank a activate command for bank a read command for bank a read command for bank a read command for bank a activate command for bank a read command for bank a t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa1 qaa2 qaa3 qaa4 qab1 qab2 qac1 qac2 qac3 qac4 h raa raa caa cac caa raa cab ba0 raa l hi-z [burst length = 4, /cas latency = 3] clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa1 qaa2 qaa3 qaa4 qab1 qab2 qac1 qac2 qac3 qac4 qad1 qad2 qad3 h rad raa cad cac caa rad cab ba0 raa precharge command for bank a activate command for bank a read command for bank a read command for bank a read command for bank a activate command for bank a read command for bank a l hi-z [burst length = 4, /cas latency = 2]
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 50 random column write clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z dda1 dda2 dda3 dda4 ddb1 ddb2 ddc1 ddc2 ddc3 ddc4 h rdd rda cdd cdc cda rdd cdb ba0 rda ddd1 activate command for bank d write command for bank d write command for bank d write command for bank d precharge command for bank d activate command for bank d write command for bank d ddd2 [burst length = 4]
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 51 random row read clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z qba1 qba2 qba3 qba4 qba5 qba6 qba7 qba8 qaa1 qaa2 qaa3 qaa4 qaa5 h rbb rba cbb caa cba rbb raa rba raa qaa6 qaa7 ba1 activate command for bank b read command for bank b activate command for bank a read command for bank a precharge command for bank b activate command for bank b read command for bank b precharge command for bank a [burst length = 8, /cas latency = 3] clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z qda1 qda2 qda3 qda4 qda5 qda6 qda7 qda8 qba1 qba2 qba3 qba4 qba5 h rdb rda cdb cba cda rdb rba rda ba0 rba qba6 qba7 qba8 activate command for bank d read command for bank d activate command for bank b read command for bank b precharge command for bank d activate command for bank d read command for bank d [burst length = 8, /cas latency = 2]
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 52 random row write clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 daa3 daa4 daa5 daa6 daa7 daa8 dda1 dda2 dda3 dda5 dda6 dda7 h raa cab cda rda raa rda dda8 dab1 dab2 rab daa1 daa2 ba0 caa rab activate command for bank a write command for bank a write command for bank d activate command for bank d precharge command for bank a activate command for bank a precharge command for bank d write command for bank a l hi-z dda4 [burst length = 8]
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 53 read and write clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa1 qaa2 qaa3 qaa4 dab1 dab2 qac1 qac2 h raa cac cab dab4 caa raa ba0 activate command for bank a read command for bank a write command for bank a 0-clock latency read command for bank a word masking write latency = 0 l hi-z hi-z at the end of wrap function 2-clock latency [burst length = 4, /cas latency = 3] clk cke /cs /ras /cas /we ba1 a10 add dqm dq activate command for bank a read command for bank a write command for bank a 0-clock latency 2-clock latency read command for bank a t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 qaa1 qaa2 qaa3 qaa4 dab1 dab2 qac1 qac2 qac4 h raa cac cab dab4 ba0 caa write latency = 0 raa word masking l hi-z hi-z at the end of wrap function [burst length = 4, /cas latency = 2]
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 54 interleaved column read cycle clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z aa1 aa2 aa3 aa4 da1 da2 dc1 dc2 ab3 ab4 h ab1 ab2 db1 db2 raa rda ba0 raa cab cdc rda cda caa activate command for bank a activate command for bank d read command for bank d read command for bank d read command for bank d read command for bank a precharge command for bank d precharge command for bank a read command for bank a cdb [burst length = 4, /cas latency = 3] clk cke /cs /ras /cas /we ba1 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z aa1 aa2 aa3 aa4 da1 da2 dc1 dc2 dd1 dd2 dd3 dd4 h raa rda ab1 ab2 db1 db2 ba0 raa rda caa cda cdb cdc cab cdd activate command for bank a activate command for bank d read command for bank d read command for bank d read command for bank d read command for bank a read command for bank d precharge command for bank a precharge command for bank d read command for bank a [burst length = 4, /cas latency = 2]
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 55 interleaved column write cycle clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z aa1 aa2 aa3 aa4 ba1 ba2 bc1 bc2 bd1 bd2 h ab1 ab2 bb1 bb2 raa rba raa cab cbc rba cba cbb caa cbd bd3 bd4 activate command for bank a write command for bank a activate command for bank b write command for bank b write command for bank a precharge command for bank a precharge command for bank b write command for bank b write command for bank b write command for bank b ba1 [burst length = 4]
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 56 auto precharge after read burst clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h rdb raa raa cab caa rdb cda rda cdb hi-z ba1 rda activate command for bank a activate command for bank d read command for bank a read with auto precharge command for bank d read with auto precharge command for bank a read with auto precharge command for bank d auto precharge start for bank d activate command for bank d auto precharge start for bank a [burst length = 4, /cas latency = 3] clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h ba1 rdb rac rda raa raa cab caa rdb cda rda cac cdb rac hi-z activate command for bank a activate command for bank d read command for bank a read with auto precharge command for bank d read with auto precharge command for bank a auto precharge start for bank d read with auto precharge command for bank d auto precharge start for bank a auto precharge start for bank d activate command for bank a read with auto precharge command for bank a activate command for bank d
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 57 [burst length = 4, /cas latency = 2] auto precharge after write burst clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h rdb raa raa cab caa rdb cda rda cdb rda ba1 hi-z activate command for bank a write command for bank a activate command for bank d write with auto precharge command for bank d write with auto precharge command for bank a auto precharge start for bank d auto precharge start for bank a activate command for bank d write with auto precharge command for bank d [burst length = 4]
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 58 precharge termination clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l hi-z h ba1 raa rab caa raa rab cab daa1 daa2 daa3 qab1 qab2 qab3 qab4 hi-z activate command for bank a activate command for bank a write command for bank a pre termination of burst precharge command for bank a precharge command for bank a activate command for bank a read command for bank a pre termination of burst daa4 daa5 write masking rac rac t rcd t rp t ras t dpl t ras [burst length = 8, /cas latency = 3] clk cke /cs /ras /cas /we ba0 a10 add dqm dq t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 l h ba1 hi-z raa rab caa raa rab cab daa1 daa2 daa3 daa4 daa5 qab1 qab2 qab3 qab4 qab5 activate command for bank a activate command for bank a write command for bank a pre termination of burst pre termination of burst precharge command for bank a activate command for bank a read command for bank a precharge command for bank a hi-z write masking rac rac t rcd t dpl t rp t ras t ras [burst length = 8, /cas latency = 2]
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 59 package drawing 90-ball fbga solder ball: lead free (sn-ag-cu) 90- f 0.4 0.05 9.0 0.1 1.6 0.08 s 0.2 s 1.40 max. 0.27 0.03 s b a 1.3 0.8 0.8 0.9 eca-ts2-0120-01 13.0 0.1 index mark index mark unit: mm 0.2 sb f 0.08 msa b 0.2 sa 89 37 56 4 12 b a d c f e h g k j m l p n r
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 60 recommended soldering conditions please consult with our sales offices for soldering conditions of the edl5132cbma. type of surface mount device edl5132cbma: 90-ball fbga < lead free (sn-ag-cu) >
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 61 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
edl5132cbma preliminary data sheet e0490e30 (ver. 3.0) 62 m01e0107 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, users are instructed to contact elpida memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] this product is not designed to be resistant to electromagnetic waves or radiation. this product must be used in a non-condensing environment. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.

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